The invention relates generally to a low noise RF frequency synthesizer, and in particular to a quiet, inexpensive IF reference loop for an RF synthesizer which gives very low phase noise levels at a relatively low cost.
A well-known tradeoff in synthesizer design is between frequency resolution on one hand and phase noise or spectral purity on the other. The problem arises because the noise content of a signal increases somewhat linearly as the bandwidth of the signal increases. Thus, for a synthesizer with a given frequency range, increasing the frequency resolution results in an output signal with higher phase noise.
To achieve a reasonable frequency range with good resolution and low phase noise, synthesizers have used a series of phase-looked loops generating successively narrower frequency ranges and equivalent bandwidths. In order to achieve 1.0 Hz resolution over 1000 to 1500 MHz, five or six separate loops have typically been required. The frequencies are generated by multiplying a reference frequency through a series of multipliers and using summing loops for each frequency range. One technique uses a fractional-N summing loop for the final high resolution loop. The main disadvantage of these synthesizers has been that many loops are required to provide both the desired low noise signal, high resolution and wide frequency coverage at the same time. This increases the cost and complexity of the synthesizer.
An object of the invention is to provide a relatively low cost synthesizer that produces a low noise, high resolution signal over a wide frequency range.
Another object of the invention is to provide a synthesizer that produces the desired output signal using fewer phase-locked loop circuits than currently known devices.
A further object of the invention is to provide a synthesizer whose output signal contains the prime factors up to five in its divisor, so that the synthesizer's output signal can be multiplied by any of those factors without producing a fractional frequency result.
In accordance with the preferred embodiment of the invention, a relatively low cost synthesizer achieves 1.0 Hz resolution over a 1000 to 1500 MHz frequency range with a low phase noise output signal using only three phase-locked loops. The base RF signal, 980 to 1520 MHz in 20 MHz steps is generated by one loop, while the high resolution IF signal is generated by a fractional-N loop. The RF and IF signals are combined in a third phase-locked loop, the output sum loop, to produce the output signal. A programmable variable divider divides the IF output frequency, achieving coverage over the necessary frequency range by changing the divide number. The fractional-N circuit thus only has to fill in the fine steps between the divide numbers, with the largest bandwidth requirement being the range between the two lowest divide numbers. This reduces the effect of the noise from the IF reference loop because the coverage obtained by increasing the divide number reduces noise in contrast to the other techniques for increasing frequency coverage which increase noise.
Another aspect of the invention is the use of a reference frequency in the fractional-N loop that has each of the factors 2, 3, and 5 in its divisor. This is accomplished by substituting a divide-by-96 circuit where a divide-by-100 would normally be used. The result is that the output signal of the synthesizer can be multiplied by any of these factors without producing a fractional frequency.